Field
The present disclosure generally relates to a frequency-comparison circuit. More specifically, the present disclosure relates to a frequency-comparison circuit that includes a pipeline that operates asynchronously and provides output signals that specify adjustments to input clocks so that their fundamental frequencies converge on a common value.
Related Art
Phase-locked loops (PLL) are well-known and widely used feedback circuits. In these feedback circuits, the output of a local oscillator is typically divided down and compared to a reference oscillator. The comparison result is then filtered and fed back into the local oscillator to adjust its frequency and phase. PLLs allow a stable, digital output clock to be generated based on a slower reference input clock.
As illustrated in FIG. 1, in existing PLLs the typical frequency-comparison circuit is a phase-frequency detector. The phase-frequency detector compares the relative phases and frequencies of two digital clocks, such as an input clock (Ref) and a local oscillator (LO). Output signals (‘speed up’ and ‘slow down’) are often used to adjust the local oscillator to ensure the compared clocks are at the same frequency and are kept in-phase.
Frequency-locked loops (FLLs) are also well-known and widely used feedback circuits. In FLLs, the two clocks need not be in-phase, but their frequencies must be kept the same. Thus, in FLLs, frequency-comparison circuits are deployed instead, and they are typically implemented as digital counters or frequency-to-voltage converters.
However, the phase-frequency detector in existing PLLs and the frequency-comparison circuits in existing FLLs are often implemented using synchronous circuits. These synchronous circuits can be difficult to design over a wide range of operating conditions and often increase the power consumption of integrated circuits that include existing PLLs and FLLs. For example, as illustrated in FIG. 1, phase-frequency detectors often have a non-ideal reset delay.
Hence, what is needed is an integrated circuit without the above-described problems.